3112 Rodman Street, NW
Washington DC, 20008
Email: Dorian.seagrave@rcn.com
Phone: (202) 669-5411
Seagrave, D., Seagrave, G., Godfrey, J. , Lin, M.
“SpaceCube : A Reconfigurable Computing Hardware Platform for Space Applications”
MAPLD Conference, Annapolis MD., September 2008
NASA Exceptional Achievement Award 2007
NASA ONE Award Recipient 2006
THALES COMMUNICATIONS INC 5/04 – present
Title: Principal Engineer (Military)
* Military Software Radio Application
* Architected FPGA for new MHAL and waveform applications
* Produced FPGA system, dataflow and timing diagrams
* Analysis and implementation of AMBA bus architecture of Modem Hardware Abstraction Layer (MHAL) and waveform for FPGA radio application.
* Modified and Qualified Waveform components using Matlab simulation
* Mixed Verilog and VHDL design port from Xilinx Virtex 4, FX60 to Altera Cyclone III,.
* Presented path for integration to new hardware and new VHDL applications.
* ALDEC advanced simulation tool set
PLANNING SYSTEMS INC ( QinetiQ North America) 1/08 – 4/08
Title: Senior System Analyst (Military)
* Provided system analysis and design recommendations for spread spectrum radio and GPS retransmission systems to meet strict military and Boeing requirements.
* Authored trade studies on rugged RF components and FPGA radio component cores.
* Created system diagrams
* Introduced simulation solution for end to end RF system simulation.
* Architected FPGA to be used in spread spectrum radio and GPS systems.
* Authored system technical specifications and requirements documents.
* Produced Microsoft Project GANT charts for project design proposals
GODDARD SPACE FLIGHT CENTER, NASA (Sub Contractor to SGT Inc.) 6/07 – 12/07
Title: Lead FPGA and Systems Engineer (Space)
* Successfully completed “new for SpaceFllight” FPGA implementation.
* Provided System, Hardware Design, Requirements, Documentation and Logistical support for IRAD SpaceCube project – 4 x4 inch Reconfigurable Super Computer for Space.
* Architected Dual FPGA design including: embedded microcontroller and partial re- configurability
* Authored functional specifications and other technical documentation.
* Produced timing, dataflow and high level system diagrams.
* Provided VHDL design port from development FPGA (Xilinx) to Flight FPGA (Aeroflex).
* Identified and acquired tools for “new for SpaceFllight” FPGA development and manufacturing.
* Wrote Test benches for Dual FGPA design simulation verification. Functional and post route.
* Provided Synthesis, Place & Route implementations for dual FPGA design.
SWALES AEROSPACE 12/06 – 6/07
Title: Control and Data Handling (C&DH) Avionics Box Lead (Space)
* Provided a successful quick turnaround, COTs based C&DH redesign for Space.
* Wrote requirements and managed subcontractor implementation of : Chassis construction, internal harnesses , multiple cPCI modules, multiple FPGA specifications.
* Defined C&DH interfaces and components.
* Authored C&DH Box Specification, Test Plans, and Test Procedures.
* Provided system diagrams: high level, data flow and timing.
* Defined interfaces between instruments and the custom C&DH FPGAs on cPCI modules.
* Performed low level verification / integration of C&DH Engineering Unit Custom/COTS cPCI module interfaces / FPGA functionality.
* Produced FPGA based quick turnaround EGSE to test non-standard avionics serial interfaces.
* Familiar with Flexible Bus Space Applications / Architecture.
GODDARD SPACE FLIGHT CENTER, NASA(Contractor w/ ORBITAL SCIENCES) 12/05 – 11/06
Title: Avionics IPT Lead (Space)
* Produced Avionics Architecture, System timing, and Control schemes for International Space Station (ISS)Express Logistics Carrier Project Avionics.
* Avionics Box Lead for Express Logistics Carrier. Avionics provided communications and control between the International Space Station and external devices on the Express Logistics Carrier.
* Board design: 4 x 4 ISS communications Interface module for SpaceCube which housed: Custom Fiber Optic TX and RX interface , 1553, Unique 10BaseT Internet implementation, RS422, LVDS and AeroFlex FPGAs (Mentor Graphics: DxDesigner, PADs )
* Architected Avionics A/D module using APL TRIO device.
* Xilinx Virtex 4 (VHDL), Altera Cyclone II (VHDL), Aeroflex 6325 (VHDL) ( Symplicity, Xilinx Foundation and Impact tools, Quick Logic tools, Quartus II tools) Aeroflex Summit 1553 RT & BC, DCC 1553 RT & BC
* Architecture for Virtex 4 FPGA: included high speed asynchronous data recovery by phase shifting global clock, TAXI processing for 100BaseT, 10BaseT, and serial I/O using a simple, custom protocol.
* Initial methodology concept for 802.3 Physical Interface implementation for Space. (10BaseT )
NORTHRUP GRUMMAN 4/04 – 12/05
Title: Avionics Box Lead (Military)
* Box level system design and requirements for proof of concept avionics radar
* Adapted existing single receiver system to process data for three independent receivers. This included minor hardware modifications, faster clocks and new FPGA implementations on three existing modules.
* Architected 4 Xilinx Virtex FPGAs in the system: implemented 3 partially, 1 completely. ( Symplicity, ModelSim, Xilinx Foundation tool set)
* FPGA Architectures included: 1553 RT, asynchronous high speed pulse detection, portions of a dynamic FIR filter, data processing, remote A/D control, parallel and serial bus interfaces, shared memory, FIFOs, implementation of complicated algorithms, discretes and VME.
* Critical discrete signals and data processing required careful analysis of clock distribution delays, component delays , FPGA design delays, and trace delays between components.
* Designed module and box level tests
* Mentor for group of new graduates
THALES COMMUNICATIONS (RACAL AVIAONICS) 1/02 - 4/04
Title: Senior Hardware Engineer (Military)
* Avionics Camera Data Processing Unit: Converted NTSC camera data to digital stream and provided output resolution options used on different aircraft avionics monitors. (Combination of COTS and digital design)
* Motherboard design containing CPCi, LVDS and high power interfaces (Orcad, PADs)
* Produced the FEMA (Failure Event Mode Analysis) on avionics system
* Altera FPGA design (VHDL) controlling avionics video, communications and power
* Lattice FPGA (VHDL) implementation of video mixing and synchronization
* Implemented decoding and de-interlacing of composite NTSC square pixel video
* Implemented progressive video scaling
* Authored board and system level documents
* Performed board and system level testing.
HUGHES NETWORK SYSTEMS 1/98 - 9/01
Title: Digital Board Lead (Commercial)
* Designed the first board in the company to use cPCI, Hot Swap, BGAs and very small footprint surface mount components. I was responsible for guiding the place & route, and manufacturing of the new technology.
* Designed digital communication board for ground station satellite radio transmit and receiver modules which included: FPGAs (Altera), CompactPCI interface (PLX PLC9030 bridge), and CompactPCI High Availability Hot Swap capability.
* Altera 6024A FPGA (Verilog) architecture included: dynamic control of PLLs, Automatic Gain Control , A/Ds and DACs. (I2C and SPI interfaces)
* Wrote Earth Station Gateway Controller/Transceiver Hardware Specifications
* Developed the System Hardware Verification Test Plan. Wrote Earth Station Commissioning Hardware Test Procedure and managed test software development. The Test Procedure and software was used by Earth Station Commissioning teams worldwide. ICO and Thuraya mobile telephone satellite systems.
* Familiar with Time Division Multiple Access and Wideband TDMA
* Experience with E1 and T1 line protocols and hardware
Deniz Corporation 6/95 - 12/95
Telesciences CO Systems Inc 3/89 - 10/92
Temple University
Bachelor of Science in Electrical Engineering 1987
Women’s Olympic Judo Team Finalist 1980